Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
نویسندگان
چکیده
An efficient automatic test pattern generator for IDDQ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Genetic algorithms are used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented.
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تاریخ انتشار 1996